Δ∑ Fractional-N Synthesizer for DCS-1800 Frequency Standard

چکیده مقاله

This paper presents an integrated phase-locked loop (PLL) frequency synthesizer for wireless communication application in standard 0.18 µm CMOS process. Delta sigma modulator used for reducing phase noise. The use of  modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractionalPLL techniques. Simulation results show that the phase noise of frequency synthesizer is -118@1MHz offset, and the PLL synthesizer provides output frequencies 1710-1785 MHz in uplink and 1805-1880 MHz in downlink. F_ref is 86.4 MHz and channel spicing is 200 KHz. Moreover, benefiting from the combination of current-mode-logic (CML) the PLL consumes a total power dissipation of only 24.50 mW with a single 1.8 V supply including all the buffers. Although prescaler increases settling time (ts), it decreases power consumptions. Settling time in uplink is 400 ns and in downlink about 380 ns.

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